Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog standard

Search list

[VC/MFC] report

Description: Report about ATA standard that implement by verilog
Platform: | Size: 18432 | Author: pepekeke | Hits:

[VHDL-FPGA-Verilog] I2C_Controller

Description: 对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656
Platform: | Size: 1024 | Author: 黄涛 | Hits:

[Compress-Decompress algrithms] H.264

Description: H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
Platform: | Size: 827392 | Author: liu | Hits:

[VHDL-FPGA-Verilog] iic

Description: 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
Platform: | Size: 306176 | Author: PUDN_CHEN | Hits:

[VHDL-FPGA-Verilog] IEEEStd1364_2001

Description: verilog 1364——2001 语言标准-Verilog Hardware Description Language standard
Platform: | Size: 2178048 | Author: yangsher | Hits:

[VHDL-FPGA-Verilog] hello_flash

Description: hello_flash是ALTERA的NIOSII核的标准程序。读写FPGA外带的Flash。-ALTERA the hello_flash is standard procedure for nuclear NIOSII. Hit-and-run of the FPGA to read and write Flash.
Platform: | Size: 1024 | Author: 王祥以 | Hits:

[VHDL-FPGA-Verilog] des_Vhdl

Description: VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
Platform: | Size: 47104 | Author: changjc | Hits:

[Software Engineering] DDCFPGA

Description: 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T receiver machine multi-rate DDC module, and the simulation in the FPGA implementation. Numerical oscillation in the complex mixer module, based on the input signals of different bandwidths (6M/8MHz) choose a different group of complete decimation filter extracted factor 3 or 4 of the multi-rate processing tasks, using two half-band filter (HBF) cascade to complete four times decimation filter, single-stage Chennai Nyquist filter to complete three times the decimation filtering.
Platform: | Size: 309248 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] DES

Description: This is verilog source code for DES(Data Encryption standard) which is used in network security.
Platform: | Size: 20480 | Author: Krupesh | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[Other] verilog-ieee

Description: verilog 2001 LRM.IEEE standard.
Platform: | Size: 2181120 | Author: muylor | Hits:

[RFID] 2

Description: RFID系统的IEEE的文章，安全协议，认证- In this paper, we first propose a cryptographic authentication protocol which meets the privacy protection for tag bearers, and then a digital Codec for RFID tag is designed based on the protocol. The protocol which uses cryptographic hash algorithm is based on a three-way challenge response authentication scheme. In addition, we will show how the three different types of protocol frame formats are formed by extending the ISO/IEC 18000-3 standard[3] for implementing the proposed authentication protocol in RFID system environment. The system has been described in Verilog HDL and also synthesized using Synopsys Design Compiler with Hynix 0.25 µ m standard-cell library. From implementation results, we found that the proposed scheme is well suite to implement robust RFID system against active attacks such as the man-in-the-middle attack.
Platform: | Size: 233472 | Author: fxy | Hits:

[Software Engineering] IEEE_Verilog_2001

Description: Verilog 2001 编程规范中文版，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
Platform: | Size: 2236416 | Author: 徐杰猛 | Hits:

[Other] H6502

Description: H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块和著名的6502的软件源码-The standard H.264 decoder all verilog source code, including the frame, frame, transform coding, entropy coding, filtering all modules and the famous 6502' s software source code
Platform: | Size: 75776 | Author: 黄奇家 | Hits:

[Other] Verilog_HDL

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: lucer_29a | Hits:

[VHDL-FPGA-Verilog] fpu100_latest.tar

Description: 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Platform: | Size: 1981440 | Author: 赵恒 | Hits:

[VHDL-FPGA-Verilog] Verilog_HDL_Synthesis_A_Practical_Primer

Description: verilog综合经典教程，verilog标准制定人写的书，推荐-verilog synthesis classic tutorials, verilog standard-setting people write books, recommended
Platform: | Size: 4981760 | Author: huizi | Hits:

[VHDL-FPGA-Verilog] IIC

Description: 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
Platform: | Size: 3072 | Author: 吴梁辛 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
Platform: | Size: 79872 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] i2c

Description: 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
Platform: | Size: 3072 | Author: wangminghui | Hits:
« 1 2 34 5 6 7 8 9 »

CodeBus www.codebus.net